A full-parallel implementation of Self-Organizing Maps on hardware

Self-Organizing Maps (SOMs) are extensively used for data clustering and dimensionality reduction. However, if applications to fully benefit from SOM based techniques, high-speed processing is demanding, given that tends be both highly dimensional yet “big”. Hence, a parallel architecture the introduced optimize system’s time. Unlike most literature approaches, proposed here does not contain sequential steps — common limiting factor speed. The was validated on FPGA evaluated concerning hardware throughput use of resources. Comparisons state art show speedup 8.91× over partially serial implementation, using less than 15% resources available. Thus, method points will obsolete quickly.